SYou1New Contributor6 years agoDDR3 IP internal Timing problem 客户使用DDR3 IP的做了一个最小系统，使用了全部6个port，每个port时钟都不一样，现在每个时钟（都小于125Mhz）到IP内部的时钟都出现了时序问题。请问下IP内部是如何同步时钟的？是否能忽略 谢谢
Recent DiscussionsF-Tile xcvr placement on DK-DEV-AGF023FAMAX10 TSE reference designCyclone-V SCFIFO with M10K/MLAB memory - adding ECCConstraints not being picked for DCFIFOCyclone 10 GX IBIS-AMI models
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