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Altera_Forum's avatar
Altera_Forum
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11 years ago

DDR3 ip controller

Hi, I am working on DDR3 uniphy IP controller. I have generated IP controller and added Timing parameters asper the datasheet and generated it. I opened the example design as my top module and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

This issue i have solved by reducing the memory clock speed to below 300MHz. Before entering Memory parameters we should check the maximum memory speed grade of our FPGA using altera memory spec estimator.

Thanks & regards,

C. Ashok reddy