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Altera_Forum
Honored Contributor
11 years agoDDR3_CONTROLLER problem
Hi, There is an error when I complie the DDR3 controller simulation design: Error (17044): Illegal connection found on I/O input buffer primitive DDR3_example_sim_e0:e0|DDR3_example_si...
Altera_Forum
Honored Contributor
11 years agoAre you sure the dynamic control should be ground? If you did not chane it, then ok
Next thing, the error means that component there, is making an illegal conection, perhaps it is bidirectional and it is connected to something unidirectional outside. Perhaps it is connected to the wrong type of pin, perhaps it is connected to multiple pins outside on your top level (note that the second error says it "also drives out other destination than the buffer"). Here is the help saying what that means: http://quartushelp.altera.com/13.1/mergedprojects/msgs/msgs/escl_scl_illegal_wys_io_ibuf.htm Perhaps one of these gives you a hint, someone had this on a Stratix IV part: http://www.alteraforum.com/forum/showthread.php?t=5825