DDR3 controller issue

Thanks for helping out

1. Its one generated from megawizard.

2. Yes all timing constraints meet.

Another issue; once the controller starts troubling, the data which is supposed to be on address 0 appears at address 1 and the data that should be on address 1 appears at address 2

For example If I assert burst begin for a cycle with read req, transfer size of 16 256-bit words with address equal to zero. I receive an unexpected value at first valid beat and the second beat contains the word that should be on the first beat.

I doubt that it may be due to unstable burst-begin signal that deasserts before avl_ready. I haven't captured that scenario in signalTap but once I get the first wrong data I always get the wrong data. I have tried 100s of read

I will try to get the DDR3 model and simulate it in Modelsim

Thanks CoworthRS