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Altera_Forum's avatar
Altera_Forum
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16 years ago

ddr2 write/read problem

the control signals are came out correctly(read/write req, read/write data valid). but the read out data are not correct(compared with the witten data). I use the example_top (ddr2 hp v7.2) as the to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I think you misunderstand me.I don't probe DQ.DM,DQS pins with signaltapII, I probed the registers in my ddr2 controller datapath. I don't understand why this problem come up too.