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Altera_Forum's avatar
Altera_Forum
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16 years ago

ddr2 write/read problem

the control signals are came out correctly(read/write req, read/write data valid). but the read out data are not correct(compared with the witten data). I use the example_top (ddr2 hp v7.2) as the to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I got the same problem as you.

I use the ALT_DQDQS as the MEMORY interface , quartus encounter a internal error when assembler process if I probe the data output from ALT_DQDQS by SignalTapII.

And I tried to use ALTMEMPHY megafunction ,but till now, it can't be simulated successfully, and it sames that the calibration process was unsuccessful.

Is any somebody can help us??Thank you very much.