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Altera_Forum
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14 years ago

DDR2 with Uniphy Calibration

Hello, I'm trying to get a DDR2 interface up and running. The hardware seems to work fine when I use the EMIF toolkit. Calibration and margining tests pass with flying colors. Now when I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi BadOmen,

Thank you for taking a look at my project. I took my own advice and used SignalTap on several of my reset signals and it looks like afi_reset was part of the problem. I couldn't find any examples that used a different clock domain for the DDR2 interface in Qsys so I was just trying to piece it together myself. You don't happen to have any experience getting the CSR to read so you can use the full functionality of the EMIF toolkit do you? :D

I've attached the working qsys file, hopefully it can help someone avoid that mistake in the future. Not saying it's the best design but it does work. Change .txt to .qsys.

Thanks again,

Scott