DDR2 with Uniphy Calibration

I've partially solved the calibration part on the Stratix IV I'm using. The key for me was the reset structure. If you signaltap the DDR interface and look at the resets, pll lock, and status signals (local_cal_success, local_cal_fail, local_init_done) then it could give you some indication of where the breakdown is happening.

I've got a simple project with the avl clock coming out of the DDR2 interface driving the whole system. Now that works so I'm trying to separate the DDR2 clock domain from everything else using a clock crossing bridge. Still working through that now.

If you throw your qsys file up, I'll take a quick peek to see if anything jumps out at me. I'll put my simple one up in case it can help you. Just change it to .qsys since the forum won't let me post that file type directly.

Regards,

Scott