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Altera_Forum
Honored Contributor
Honored ContributorDDR2 with Cyclone V
Have anyone been able to control a DDR2 SDRAM using the UniPHY Megacore IP from Cyclone V?? Im trying to do so, I have use this same memory with a Cyclone III before and im using the same circu...
Altera_ForumHonored Contributor
Honored ContributorCan you try to reduce the interface speed for example from 400MHz to 200MHz?
And full compilation did you see any timing violation reported inside Quartus II?
