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Altera_Forum's avatar
Altera_Forum
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12 years ago

DDR2 with Cyclone V

Have anyone been able to control a DDR2 SDRAM using the UniPHY Megacore IP from Cyclone V?? Im trying to do so, I have use this same memory with a Cyclone III before and im using the same circu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Helo,

Do you have our Cyclone V dev kit? Did you try to run the simulation first using the generated example design? Make sure the PHY calibration is passing as well as the user mode (read / write).

After that you may jump into hardware testing and you may use the EMIF toolkit to check if your design is working.

Hope this helps.