DDR2 VHDL Simulation model for Altera DDR2 controller

Ok, got it working with the Free Model Foundry Model mt47f256m4, though there was an error in write burst timing that I had to fix.

If you try the same look out for this assignment:

In_data <= '0',

'1' AFTER 3*CK_period/4 - 0.5 ns;

and change it into this assignment:

In_data <= '0',

'1' AFTER 7*CK_period/4 - 0.5 ns;

I did not think about it in greater detail, maybe the problem does not arise with higher clock frequencies than the 156.25 MHz I use.

flintstone