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Altera_Forum
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14 years ago

DDR2 VHDL Simulation model for Altera DDR2 controller

Hi, I am looking for a DDR2 simulation model in VHDL (due to license restrictions) that will work with the ALtera DDR2 controller. The controller was implemented by somebody else, is verified t...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Meanwhile I tried with a Free Model Foundry Model and it does not work either, but the error symptoms are different, now during calibration only one write and one read is performed. I have no idea how to debug this issue but I will try further. The whole algorithm that I am trying to develop relies scheduling DDR2 readout vs sending the data over an external interface. I need a working DDR2 memory model to verify this.

Really, this might not be the right place for mourning, but these things belong to a working ecosystem for a developer. And it can't be too hard to provide some generic memory model to be able to simulate a standard system without paying high license fees just to be able to include the state of the art memory component in the development process.

Best regards,

flintstone