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Altera_Forum
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15 years ago

DDR2 User Controlled Refresh

Hi, My name is Hardik Shah. I am using Cyc3 Dev board for my work. I have the following questions. I am using high performance controller. i) The document "External Memory Interface H...
Altera_Forum's avatar
Altera_Forum
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15 years ago

SDRAM usually have a refresh controller, so You have to assert a special pin combination (e.g. CS,RAS,CAS low, WE high and a last address high), then the self-refresh of all the rows occours. I am not sure about the sequence I've mentioned, that was only an example.