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Altera_Forum
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14 years ago

DDR2 User Controlled Refresh

Hi, My name is Hardik Shah. I am using Cyc3 Dev board for my work. I have the following questions. I am using high performance controller. i) The document "External Memory Interface H...
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Altera_Forum
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14 years ago

From a micron data sheet

"The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command."

I believe this is a just a sequential counter, so you cant refresh part of the memory. I'm not aware of any way around this.