Forum Discussion
Altera_Forum
Honored Contributor
15 years agoDDR2 User Controlled Refresh
Hi, My name is Hardik Shah. I am using Cyc3 Dev board for my work. I have the following questions. I am using high performance controller. i) The document "External Memory Interface H...
Altera_Forum
Honored Contributor
15 years agoi) SDRAM requires a refresh every 64ms. This is done a row at a time, usually there are 8192 rows so if you space these out evenly you need to do a refresh every 7.8us. However, JEDEC spec for SDRAM allows you to do up to 9 row refreshes back to back, thus allowing a longer period before doing another batch, which may help with efficiency in some systems
ii) minutes is not that unusual under ideal conditions, tens of minutes would be. iii) refresh is done on a per row basis iv) only a row is refreshed, so i think what they mean by burst is doing up to 9 as mentioned above