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Altera_Forum
Honored Contributor
10 years agoDDR2 UniPhy OCT
Hi, I am using DDR2 Uniphy and get an Error on calibrated OCT: I run tcl after synthesis and tcl run successfully as qsf updated, for instance DDR IO constrained properly : "set_instan...
Altera_Forum
Honored Contributor
10 years agoHave you tried setting OUTPUT_TERMINATION "SERIES 50 OHM with CALIBRATION" instead? Your bidir DDR2_DQ have parallel termination with calibration during input, yet during outputs it doesn't use it.