Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDDR2 Troubles on Cyclone III
I'm having some trouble with DDR2 interface on a Cyclone III system. I'm using v. 9.1 of the tools, SOPC builder with the Legacy High Performance Full Speed Controller, 133MHz memory clock. The mem...
Altera_ForumHonored Contributor
Honored ContributorNo, the same clock domains.
In the memory presets, we can specify the number of clocks. In this case, there are two. The clocks should be on the same domain. The clocks each go to one of the ICs. For what it is worth, the lower byte of the each of the ICs is being read correctly and consistently. I would expect a clock domain issue to result in in a error in the upper and lower bytes in one or both of the ICs.
