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Honored Contributor
Honored ContributorDDR2 Troubles on Cyclone III
I'm having some trouble with DDR2 interface on a Cyclone III system. I'm using v. 9.1 of the tools, SOPC builder with the Legacy High Performance Full Speed Controller, 133MHz memory clock. The mem...
Altera_ForumHonored Contributor
Honored ContributorSo that means that all data and ctrl signals are related to one of the clocks?
That will never work unless the IP actually supports that. My guess is that the lower bytes is the chip with the controller clock. You need to use a clock from the same pll, maybe with a few degrees tune... I mean, you have two totally different clock domains here....?
