DDR2 Troubles on Cyclone III

Hi,

I am in the middle of Win7-64 / Nios Eclipse 10.0 and find everything regarding altera cumbersome these days...about to install linux. Ungodly slow in windows.

The bridges are essential in order to separate clock domains, ease timing req and so on.

If you do run a bunch of low speed PIOs you may separate those from the high speed CPU/memory/cache clock domain.

All of our Nios/DDR designs have:

CPU

Cache

On chip ram

JTAG

In the DDR_AUX half rate or full rate clock

and the rest is run at 10MHz using a clock separation bridge.

BUT, anything that your CPU is constantly accessing should be put in the high speed domain. That is for you to decide.

The embedded design handbook is actually quite good, you should have a look. We have designed multi core systems that has been running flawless for 4 years now based on that information.

I don't do much low level work these days, but it happens. Maybe some of the gurus can take you further.

apus