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Altera_Forum
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15 years ago

DDR2 Troubles on Cyclone III

I'm having some trouble with DDR2 interface on a Cyclone III system. I'm using v. 9.1 of the tools, SOPC builder with the Legacy High Performance Full Speed Controller, 133MHz memory clock. The mem...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

gabrigob - This is real world, not simulation. I've run the identical design on the Cyclone III 125 dev kit, and have no problems. I've not notices any issues with the instantiation.

agdepus - Thanks. This appnote looks helpful, and not a;; that cumbersome. I'm currently using Nios memtest project to read/write to memory. I don't quite understand what you mean by bridge - can you elaborate?