Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DDR2 Troubles on Cyclone III

I'm having some trouble with DDR2 interface on a Cyclone III system. I'm using v. 9.1 of the tools, SOPC builder with the Legacy High Performance Full Speed Controller, 133MHz memory clock. The mem...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the X in the read back are because there is a randomization on the read result in hardware or because this is the result of a simulation?

I had once a problem with the data stored in DDR2 memory that time I changed the name of the controller instance in SOPC Builder but forgot to reapply assignments and re-check timing constraints; the name of the ports in the SOPC Builder instance changed losing relation with the pins of the top level design.