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Altera_Forum's avatar
Altera_Forum
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16 years ago

ddr2 tco skew to high?

I generated a ddr2 controler with cyclone2 ip core. when i full complation used quartus2 7.2, it warning TCO skew between clock to sdram pins too high at 135ps. how to solve it? THANK YO...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The simple answer is to manually place the clk output pins. They all need to be on the same type of pin, differential clock output pairs are a good choice