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Altera_Forum
Honored Contributor
Honored ContributorDDR2 SDRAM with UniPHY not generating half_rate_clock
Hi there, I'm using Quartus 12.1 SP1 and generated a DDR2 SDRAM Controller with UniPHY via the MegaWizard Plugin Manager. The Memory Frequency is 400 MHz, PLL reference clock 50 MHz and the Rate...
Altera_ForumHonored Contributor
Honored ContributorFWIW, I can confirm the above; these are my observations (Quartus 12.1 sp1, 12.1 uniphy, ddr2, stratix III)
o the afi clock is active, hopefully it runs at half rate if its a half rate uniphy and at full rate if its a full rate uniphy consistent with the Uniphy functional description doc o the afi half clock always runs at 0 Hz, independent of whether its enabled or not in the megawizard gui
