Forum Discussion
Altera_Forum
Honored Contributor
17 years agoI remember that I had a similar issue with a SODIMM DDR2 design, I even used ModelSim to understand the initialisation steps and observable signals. But it turned out as very basic wiring fault that would have been detected by checking the design more thoroughly. Usual timing problems are rather causing data errors than calibration failure.
As you probably know, DDIO pins are accessible with SignalTap, so you can't easily debug DDR RAM operation.