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Altera_Forum
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14 years ago

DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

Hi,

I am trying to generate a DDR2 SDRAM Controller for a single 128 MB DDR2 chip. QSYS perform a good generation (6 warning wich don't concern the ddr2 Controller) but when i try to synthesis the project i have this error :

Error: Output port DATAOUT of DDIO_OUT primitive "nios2_ca1_sys:nios2_sys_inst|nios2_ca1_sys_ddr2:ddr2|nios2_ca1_sys_ddr2_controller_phy:nios2_ca1_sys_ddr2_controller_phy_inst|nios2_ca1_sys_ddr2_phy:nios2_ca1_sys_ddr2_phy_inst|nios2_ca1_sys_ddr2_phy_alt_mem_phy:nios2_ca1_sys_ddr2_phy_alt_mem_phy_inst|nios2_ca1_sys_ddr2_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_outa[0]" must drive input port I of an I/O OBUF primitive

I suspect it to be a reset problem of the controller because, before this error i have those warnings :

Warning: The following bidir pins have no drivers

Warning: Bidir "Ddr2_Clk_P[0]" has no driver

Warning: Bidir "Ddr2_Clk_N[0]" has no driver

Warning: Output pins are stuck at VCC or GND

Warning (13410): Pin "Ddr2_Cke[0]" is stuck at GND

Warning (13410): Pin "Ddr2_Cs_N[0]" is stuck at GND

Warning (13410): Pin "Ddr2_Odt[0]" is stuck at GND

In QSYS i have connected soft_reset_n and global_reset_n inputs of the ddr2 Controller to the clk_reset ouput of the Clock source (wich also drive the reset_n input of the Nios2).

I am stuck with this error, have i tried many reset configurations, but i still have this error...Is it realy a reset problem?

Need Help Please.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    @mlefevre Nice it worked also for you! :)

    I think if the signal is defined in the toplevel of the QSYS generated code as 

    inout  wire        bus_ssram_tcm_begintransfer_n_out
    the coresponding VHDL should be 

    bus_ssram_tcm_begintransfer_n_out               : inout std_logic
    May be there are some signals defined as 

    inout  wire        some_signal
    then it would be 

    some_signal               : inout std_logic_vector(0 downto 0)
    But here I'm not sure because I never wrote Verilog...

    Anyway, the SOPC Builder created also VHDL Code, so such problems where never there...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Anyone can summarize the final solutions? which signals in which files should I change?

    Thank you very much!