DDR2 SDRAM Controller with ALTMEMPHY Synthesis error

@mlefevre Nice it worked also for you! :)

I think if the signal is defined in the toplevel of the QSYS generated code as

inout  wire        bus_ssram_tcm_begintransfer_n_out

the coresponding VHDL should be

bus_ssram_tcm_begintransfer_n_out               : inout std_logic

May be there are some signals defined as

inout  wire        some_signal

then it would be

some_signal               : inout std_logic_vector(0 downto 0)

But here I'm not sure because I never wrote Verilog...

Anyway, the SOPC Builder created also VHDL Code, so such problems where never there...