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Hi,
My problem is that when I read memory, the two lasts words are bad and all others are good. Every time. If my pattern is 10 words long, I read back 8 good words and the last two words are bad. Whatever the patterns I use (eg different length), it's always the same...
Someone have got an idea of what's it's going on ?
What can I check in my design ?
Fabrice.
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I've also conquered the same problem with the high speed DDR2 controller of the SOPC builder. Depending of the size of the FIFO's you use, the more data is buffered. Have you already tried to do some dummy accesses to the RAM? In my case, I was writing with a NIOS processor to a video frame buffer and every time the transfer was completed, the last pixels (the last written words) stay unchanged. Doing some dummy writes resolved my problem (words in the FIFO are placed to RAM after some dummy writes)...
Hopes this helps?
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