Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DDR2 read performance issue

I'm having trouble getting maximum performance of DDR2 read. According to other threads of this forum, I should get near max performance when doing sequential reads. However, I'm getting only around ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

SOPC builder no longer generates a testbench for the Uniphy DDR2 controller. For the Altmemphy DDR2 controller, it used to generate a module called <instance_name>_test_component, which read in a .dat file and gave the data to the SOPC system. It's not a simple testbench which just gives the data according to the address, but there's multiple pipeline stages with support for bursts.

What testbench did you use for your simulation??