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Altera_Forum
Honored Contributor
14 years agoAs the commands for the two chips are are issued by one controller each DRAM chip will run in sync with the other. The Altmem-PHY just sees the two chips as an aggregated DQ/DQS bus.
As the commands for the two chips are are issued by one controller each DRAM chip will run in sync with the other. The Altmem-PHY just sees the two chips as an aggregated DQ/DQS bus.