DDR2 on two sides - one controller

If you already have FIFOs I don't think you'll need an extra buffer layer. In the case of writes if only one controller is ready you can still post the write, just don't pop the FIFO until you can post the other half of the write (or you can dual buffer write commands and write the data independently...... assuming you are not worried the two FIFOs getting out of sync). In the case of the reads if you instantiated two half width FIFO's (one per controller) then you just pop the FIFO when both are not empty. This way you won't end up adding more round trip latency by double buffering the commands and data.