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Altera_Forum
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14 years ago

DDR2 on two sides - one controller

Hello, We are using an Arria II with DDR2 chips on two sides of the FPGA. Is there a way to aggregate the two and control them with one instance of the DDR2 HP controller? We are using HP and...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks BadOmen for the response!

I kind of came to the same conclusion, which is basically RAIDing the two chips using two HP instances and adding a wrapper to make it transparent.

I need to use the two chips at the same time not for the bus width but for throughput. I am not using SOPS/Qsys but have my own wrapper around the Altera phy.

As far as latency, I wonder how that would be affected if I instantiate two controllers and send the commands at the same time to both instances with each instance handling half the data. I wonder if the refresh cycles will be sync'd as the lack of that may cause extra latency.

Do you agree on my assessment?