Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDDR2 on two sides - one controller
Hello, We are using an Arria II with DDR2 chips on two sides of the FPGA. Is there a way to aggregate the two and control them with one instance of the DDR2 HP controller? We are using HP and...
Altera_ForumHonored Contributor
Honored ContributorThe most straight forward approach (I think at least) would be to create a bridge that has one wide slave port and two master ports of half the width. The bridge would be responsible for buffering wide requests and sending them to both masters to handle accessing each memory controller. For read data the bridge would be responsible for making sure both data halves return before gluing them together into a single wide word.
For all this to work I made the following assumptions: 1) You don't care about latency 2) You use SOPC Builder or Qsys to do this There are probably cleaver ways of instantiating two PHYs and one controller and rolling your own solution but that seems like a lot of monkey work to me. Also do you really need a wide interface? Could you get away with accessing each side independently?
