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Altera_Forum
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15 years ago

DDR2 HPC2 Timing Simulation fails

Hello, i am trying to get the example design for the DDR2 Memory controller (HPC2 with ALTMEMPHY) to work. I have spent already a whole week on this issue, but I cant get it to run. I am using ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I forgot to mention, that I haven't derated the memory timings (tDH, tDS, tIH, tIS) yet. I just did it and will try the new settings. Can you tell me about the slew rates of the ddr pins? Do I have to set the slew rate according to the tutorial (e.g. CLK and CLK# = 1.5 V/ns (differential))? Or is it just for derating calculations and the slew rate of these pins should remain at 3? Thank your very much.

Best regards,

Martin

EDIT:

Derating improved the signal integrity, but the problem still persists.