DDR2 HPC2 Timing Simulation fails

Hello Matthias,

Thank you for your help! I succeeded in implementing the HPC2 with my custom logic. After creating LogicLock-regions and manually reassigning a clock buffer, the timing problems disappeared. Now I have a weird problem on the hardware:

Sometimes a read-burst is split into several smaller burst (I observed this in the rtl simulation too, but there it worked fine) and not all valid words contain valid data. As you can see in the first attached signaltap waveform, the marked burst is split and only the first 2 data beats are delivered. In the rtl simulation (I attached a modelsim waveform with exactly the same address, so you can compare it) all data beats are delivered. This does not always happen. As you can see later in the waveform. In the second signaltap waveform you can see, that the burst was split in 4 parts, but there is no problem with the data. Maybe you already saw these symptoms and can explain to me why this happens and how I can fix it. Thank your very much advance!

Best regards,

Martin

EDIT:

I also encountered bit errors on the read data. I am fairly sure that the written data is correct. The read data is sometimes correct and sometimes not.