DDR2 HPC2 Timing Simulation fails

Hello Matthias,

I followed your recommendations and finally it seems to work. Unfortunately neither the DE3 manual nor the HPC2 manual lose a word about the termination block. Reading through the internet, I found information about the Rup and Rdn PINs and that they have to be connected to VCCIO and GND. Nevertheless nobody mentioned which PINs exactly, so I had to try out some locations. Doing so and reducing the clock frequency to 200 MHz (the memory can handle 333 MHz) the example design worked. Using the system clock pin as clock for signaltap removed the timing errors. Even though I will have to look for another way, since 50 MHz is very low sampling frequency. Do you know of any way to improve the memory frequency? I would really like to reach the maximum frequency of the memory, since we really need every bit of performance there. There was no timing errors when I tried 233 MHz or 266 MHz, but the calibration failed, using these frequencies. Thank you.

Best regards,

Martin