DDR2 HPC2 Timing Simulation fails

Martin,

I’m not familiar with the DE3 eval board. I am pretty sure their PCB layout allows proper DDR2 memory interfacing, so I wonder why you should see mem_clk pin location warnings.

You have to specify where your termination_blk0~_* signals are located. This is described in the HPC2 user manual.

Next make sure that you properly selected the exact DIMM parameters in the MegaWizard. Choose low speed and low CAS latencies at first. Make sure you use the exact pin locations and don’t leave the placement optional for Quartus.

When assigning signals in SignalTap, make sure you keep their number as low as possible as well as the number of samples – but don’t hesitate to raise their numbers when you have to. Don’t enable trigger functionality for signals you don’t intend to use as triggers. It’s all described in the user manual. You might want to go for a half-speed controller or half-speed interface bridge as well, to cut down timing issues.

Start at the lowest possible DDR DRAM clock frequency – typically 125 MHz – and only raise it to the max when you succeeded.

Ah, and leave out all your custom stuff for the moment. Best is to start a new project with just the DDR2 HPC2 demo app (example_top) and nothing more. Place some of the driver’s status outputs to pins that can drive LEDs or other connectors where you can connect an oscilloscope or logic analyzer. You will have so many http://www.alteraforum.com/forum//images/icons/icon3.gif enlightning events just following the standard procedure that you will have no problems doing it once more with all your custom functions around it.

Is there a demo design – even if it is binary only – for your DE3 board that can be used to verify that you don’t have any hardware issue with the chosen clock, reset, and DRAM connections?