DDR2 HPC2 Timing Simulation fails

Hi,

I put up a fresh quartus project with my custom IP cores and complete pin assignments. I added the ctl_cal_success, ctl_cal_fail and ctl_cal_warning to signaltap. Unfortunately the signal ctl_cal_fail is asserted. Quartus met the timing requirements only without signaltap. When I insert SignalTap into the design the timing fails quite miserably. I got a -4ns setup slack for:

seq_oct_oct_delay[0] => acq_trigger_in_reg

This could be the reason why the calibration fails. Would it help, if I use another clock for SignalTap? Right now I use the 100 MHz clock of my PLL. Another problem might be the following warning:

--- Quote Start ---

Critical Warning: No exact pin location assignment(s) for 2 RUP, RDN, or RZQ pins of 2 total RUP, RDN or RZQ pins

Info: RUP, RDN, or RZQ pin termination_blk0~_rup_pad not assigned to an exact location on the device

Info: RUP, RDN, or RZQ pin termination_blk0~_rdn_pad not assigned to an exact location on the device

--- Quote End ---

Do I need to connect these PINs to the design? There are no ports that I could connect them to.

Another warning I am worried about:

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Critical Warning: Memory clock pin mem_clk[0], mem_clk[1] must be placed on the same edge of the device

Critical Warning: mem_clk[0] was placed on the right edge of the device

Critical Warning: mem_clk[1] was placed on the bottom edge of the device

--- Quote End ---

How can I place the mem_clk on the same edge? The PIN assignments are fixed according to the DE3 manual.

Thank you very much in advance.

Best regards,

Martin