DDR2 HPC2 Timing Simulation fails

Do you use an evaluation kit, or is it already a custom design?

For the eval kit, you can be sure that the example design should work as described in the UG. Assure that you don’t skip any step, especially regarding constrains, pinning (mind the TCL scripts) and memory parameter file (XML). You could start with a significantly reduced memory frequency, i.e. 125 MHz for DDR2 and longer CAS latency.

I had some good experience with SignalTap checking that the PLL input clock is there (one should be able to see the oversampled lo-freq clock in the output) and see that reset is applied and released as expected – once a signal is part of the SignalTap pin list, one can quickly change the trigger condition. Next you can monitor the example driver’s I/Os (local_read_req, local_write_req, etc.) and see whether it already started driving the controller and whether it gets stuck at the first write access.

Search for ctl_cal_fail, ctl_cal_success, ctl_cal_warning deeper inside the phy part. Without calibration success, the interface will not boot up properly and will not allow any access to the memory.

Good luck.