DDR2 HPC2 Timing Simulation fails

Hi,

thank your very much for your reply. I was working with Xilinx MPMC before and I didnt expect that Altera wouldnt support timing simulation. The question now is: how can I verify my design? I tried to upload the design to the FPGA and the local_init_done signal was never asserted. I am not 100% sure if I may use this signal, since the manual suggested, that it is only for the native-interface and not for Avalon. But I needed some sort of indicator that the memory controller is ready to accept requests. Nevertheless, in the functional simulation everything was fine, so I tried to find out the error through timing simulation.

The SignalTap logic analyzer is not very well suited for debugging purposes, since I cannot access the memory pins and I can only capture a tiny time window of a few clock cycles. Additionally it has great impact on timing performance. I wasn't able to create a design that met the timing requirements. Therefore this might be the reason, why local_init_done hasn't been asserted. Is there any other way I could simulate the the memory controller with some sort of timing enabled? Thank your very much.

Best regards,

Martin