DDR2 HP Controler -- need some help!

Yes, I use DDR2 HP without SOPC system (with native interface).

For feedback signals, I check them correctly.

Really, I don't understand why I can write and read correctly continously but not with one write (in one clock cycle).

I make this test:

- I make one write at address '1' (for example)

- I wait wdata_request, I send data to write

- I wait a couple of clock cycle (maybe 15 cycles)

- Then I try read back address '1' with one read.

- I wait local_rdata_ready assert and I latch data on bus local_rdata

But I don't read the same thing I write before...

Thanks for your help Ketan. Unfortunaly, I think it's another thing...

Someone have got another idea ? Thanks!