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Honored Contributor
Honored ContributorDDR2 HP Controler -- need some help!
Hello, I'm trying to use DDR2 HP v8.0 controler. I've a stratix II PCIe dev board with 5 memory chips on it. Total memory is 288 Mo. I generate DDR2 HP with megawizard, native interface...
Altera_ForumHonored Contributor
Honored ContributorYes, I use DDR2 HP without SOPC system (with native interface).
For feedback signals, I check them correctly. Really, I don't understand why I can write and read correctly continously but not with one write (in one clock cycle). I make this test: - I make one write at address '1' (for example) - I wait wdata_request, I send data to write - I wait a couple of clock cycle (maybe 15 cycles) - Then I try read back address '1' with one read. - I wait local_rdata_ready assert and I latch data on bus local_rdata But I don't read the same thing I write before... Thanks for your help Ketan. Unfortunaly, I think it's another thing... Someone have got another idea ? Thanks!
