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First, I'm not sure if I found the right register. When I generate fan-out from the DDR_CLK pin, it send me to
...DDR_phy_alt_mem_phy_inst|DDR_phy_alt_mem_phy_mi mic:mmc|mimic_data_in_metastable[0]~feeder)
which is not in the adjacent LAB, but is almost directly in the middle of the chip (I am using a Stratix II GX ). The path is listed at 1.9 ns.
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Yes, that is the right register. The ~feeder node is inserted because Quartus has used the LUT in front of the register as the route into the register itself, rather than the SLOAD inputs. Either of these is fine, and it is simply a matter of routing which gets picked. If you look at the fanout of the ~feeder register there will be the actual ...mimic_data_in_metastable[0] register.
The fact that the register is not by the IOE is a problem though. The routing delay will mean that the mimic path will not track correctly. I guess that this is because the clock that is used for the mimic register (clk[6], as I recall) is routed on a local clock network, which only feeds one side of the chip.
The solution is to either move the PLL such that it can drive local clock on the same side of the chip as the memory interface is on, or force the mimic clock to be on a global clock network. Manually placing the mimic path register next to the clkout pin is a good thing to do, since that will either sort things out or cause a error in fitting (which can then be addressed by moving the PLL of forcing the mimic clock onto a global).
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