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You are right. The change you want to make is
set t(mimic_shift) 1.600
to
set t(mimic_shift) 2.100
It is worth checking that the mimic path register (the one that samples the clock that is driven out) is being placed close the the clock pin in the chip planner too. It should be in the first LAB in from the IOE.
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This change does allow the design to pass timing, but when I try to find the register it doesn't look like it's been placed near the IO block.
First, I'm not sure if I found the right register. When I generate fan-out from the DDR_CLK pin, it send me to
...DDR_phy_alt_mem_phy_inst|DDR_phy_alt_mem_phy_mimic:mmc|mimic_data_in_metastable[0]~feeder)
which is not in the adjacent LAB, but is almost directly in the middle of the chip (I am using a Stratix II GX ). The path is listed at 1.9 ns.
Should I be concerned about this? I'm not 100% sure if this was the path that was failing before.
Honored Contributor
