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Altera_Forum
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17 years ago

DDR2 High Perfomance Mimic Path failing timing

I am getting setup errors from the DDR_CLK to the mimic_data_in_metastable[0] path (launch clock is DDR_phy_DDR_CLK_mimic_launch_clk, latch clock is DDR_phy_ddr_mimic ). In the 9.0 errata (http...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You are right. The change you want to make is 

set t(mimic_shift) 1.600
to 

set t(mimic_shift) 2.100
It is worth checking that the mimic path register (the one that samples the clock that is driven out) is being placed close the the clock pin in the chip planner too. It should be in the first LAB in from the IOE.