Honored ContributorCan someone tell me what the definition of "chip bits" is for the local_addr field for the DDR2 SDRAM controller?
The DDR and DDR2 SDRAM High-Performance Controller User Guide says for multiple chip selects : width = chip bits + bank bits + row bits + colum bits - 1 Thanks.
Honored Contributorchip bits means the number of bits needed to drve the chip selects. A controller for a two rank memory module e. g. has one mem_local_cs_addr or chip bit, a four rank (four individual CS) has two.
Honored ContributorThanks FvM for the reply. I tried following your logic and running the Altera Megawizard Function for DDR2 High-Performance Controller. I am using a Micron MT16HTF25666H DDR2 SDRAM SODIMM that has 2 chip select bits (module rank), 10 column bits, 14 row bits, and 3 bank bits. Following the above equation, I should have 28 bits. However the Megawizard only gives me 27 bits.
Honored ContributorA signal local_addr exists neither with the stated width nor with the exact name at the DDR2 HP controller interface (also not internally, as far as I know). So far the documentation is incorrect to my opinion. Let's say, local_addr is a virtual signal.
At the controller interface, a signal local_address is present. But it has alreay been reduced by the one or two column address LSB bits, so for a 2 GByte respectively 256M x 64 DIMM module, that uses 28 address bits internally (=log2(256M) ) local_address has 27 bits for a full rate or 26 bits for a half rate controller. I'm using a DIMM module of same size and organisation with a half rate controller, and it has local_address[25:0]
