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Altera_Forum
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15 years ago

DDR2 -CYCLONE IV Termination

Hello I am designing a board which contains a DDR2 SDRAM memory and a CYCLONE IV device. I looked at the development kit of CYCLONE IV schematics and saw that all the signals from/to the ddr2 ha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You have to place termination resistor only for diff clock.

FPGA vref IO connect to DDR_VREF ( = 1.8V/2) due to io standard used DDR2.

Also you have to read ALtera documents about using DDR more carefully