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Altera_Forum
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15 years ago

DDR2 -CYCLONE IV Termination

Hello I am designing a board which contains a DDR2 SDRAM memory and a CYCLONE IV device. I looked at the development kit of CYCLONE IV schematics and saw that all the signals from/to the ddr2 ha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

hi,

I have also a small board with cyclone IV / DDR2.

When you say that DDR2 works without termination, is it only for dq/dqs or for all signals² : diff clocks, addresses and command signals ?

I also see on cyclone III dev kit that FPGA vref IO (VREFBxNy) are connected to DDR_vref. Is it needed ?

thanks.