DDR SDRA IP local address

Thank you again.

On the first time we did try to use all the 26 address line and we saw that we trying to write and read from address 0 & 1 and we find out that the data was same, after that we r that in the ddr controller paper was the next lines:

■ Full rate controllers

The width of this bus is sized using the following equation:

For one chip select:

width = bank bits + row bits + column bits – 1

For multiple chip selects:

width = chip bits + bank bits + row bits + column bits – 1

If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits

wide, then the local address is 24 bits wide. To map local_address to

bank, row and column address:

local_address[23:22] = bank address [1:0]

local_address[21:9] = row address [13:0]

local_address [8:0] = col_address[9:1]

The least significant bit (LSB) of the column address (multiples of four) on the

memory side is ignored, because the local data width is twice that of the

memory data bus width.