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Altera_Forum
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18 years ago

DDR or DDR2 SDRAM controller

I builded a DDR or DDR2 SDRAM controller using QuartusII MegaWizard Plug-In, ip toolbench. It should have self-testing function. But I can not run it in QuartusII's simulation. No DDR address, data...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

how to get the gate level file "*.vo"

my modelsim display:

** Error: (vsim-3033) E:/FPGA/video_delay/ddr2_auk_ddr_sdram.v(249): Instantiation of 'auk_ddr_controller' failed. The design unit was not found.

then I add the auk_ddr_controller.vhd(the file in the ip folder) to the work.

modelsim display :

** Error: F:/altera/72/ip/ddr_ddr2_sdram/lib/auk_ddr_controller.vhd(1): expecting: ARCHITECTURE CONFIGURATION ENTITY LIBRARY PACKAGE USE

thank you very much