DDR or DDR2 SDRAM controller

When I simulate DDR controller with ModelSim, I met the follows error.

after source ddr2_ddr_sdram_vsim.tcl

# ** Error: (vsim-3033) ../../ddr2.v(176): Instantiation of 'ddr2_auk_ddr_sdram' failed. The design unit was not found.

# Region: /ddr2test_tb/dut/ddr2_ddr_sdram

# Searched libraries:

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/220model

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/stratixii

Then I complied 'ddr2_auk_ddr_sdram' in library auk_ddr_user_lib,

after source ddr2_ddr_sdram_vsim.tcl

# ** Error: (vsim-3033) D:/work/4xHD/DDR2/ddr2_auk_ddr_sdram.v(259): Instantiation of 'auk_ddr_controller' failed. The design unit was not found.

# Region: /ddr2test_tb/dut/ddr2_ddr_sdram/ddr2_auk_ddr_sdram_inst

# Searched libraries:

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/220model

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf

# C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/stratixii

At last, I can not find 'auk_ddr_controller' code because it is altera's IP library.

How can I do simulation?