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Altera_Forum's avatar
Altera_Forum
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17 years ago

DDR local_wdata to mem_dq incorrect outpu

Hello, I need help about the proper write timing of DDR Controller, because the written data in local_bus is not properly outputed in the mem_dq. I'm not sure if the timing is correct becaus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Glad you got the problem fixed. I have no clue why altera likes to believe that these cores follow the avalone spec. It says very clearly in section 3.10.2.1 and figure 3.12 of the avalone spec(mnl_avalon_spec.pdf) that you can pause a burst write transfer by deasserting the write command. Evidently altera likes to ignore this fact and not talk about it. Oh well.